ChibiTerm - Background colour!

Projects / ChibiTerm  Original post date: 03/16/2016

I added background colour! The background colour is driven by a hardware timer output compare that is driven on during the active portion of the display. Some monitors do not like to see video signals outside of the active regions, so you can't just tie the R/G/B to 0.7V. That signal was used to tweak VGA_IRQ_Latency constant to compensate the IRQ to SPI DMA latency which affects the text alignment.

The alignment can be easily spotted on the monitor without needing a logic analyzer. Each pixels is 40ns - 2 CPU clocks. Different compilers might generate different code sequence and that could affect the timing. Using the monitor manual horizontal position control, you can shift the video to see the edges hidden at the border of the monitor. In the picture below, the text is lined up perfectly with the background.

Background colour and text alignment

Originally that pin was updated by DMA, but there is a collision with the SPI channel in the new pin assignment. I don't have the same level control as before, but I can at least turn on/off the background colour on a scan line basis. e.g. a status or menu bar or just have full background colour.

Text are still rendered in monochrome due to the lack of clock cycles and RAM. Don't expect too much of the chip.

Did some more fooling around. I can get white on grey video output by inverting the font. The latest changes in my font conversion program that brackets the font data with a C macro which makes it easy by flipping the bits there.

Grey on white output

The STM32F0 I/O pin is pretty weak (~8mA), so a buffer circuit is needed. Variation colouring scheme can be done by playing the series resistor values to the R/G/B line. This information will help me design the driver circuit.

DSView - setting up multiple cursors

Finally figure out how to set up the cursors in DSView. I have been clicking at the wrong places. A double click at the rise/fall edge of a signal adds a cursor. So obvious that it didn't need documenting. :(

I got around to finally built the buffer circuit as the STM32F0 chip output has low drive.

White on black video output (from Matrix clock demo)

There are 3 separate series resistors for the R/G/B channels and the voltage follower circuit can drive one or all three colour channels without affecting the amplitude.

Update: Black on white now works. This has something to do with the SPI getting stuck on last bit it sent out. The inverted video means that the video signal remains high and interferes with the monitor.

I padded the scanline buffer with extra 0 byte in front and back to get rid of SPI artifact and make sure that the video goes back to 0V at the end of a scan line. At some point when the other padding was added, forgot to update the byte count.

Offending line: The +2 instead of +1 there.

#define SPI_DMA_WORDS((VGA_RES_X*VGA_BITS)/SPI_WORDSIZE+2)

Black on white output