ChibiTerm - SPI RAM Buffer idea

Projects / ChibiTerm  Original post date: 03/09/2016

Here is what I had in mind originally with my SPI RAM as graphics frame buffer and why I didn't do that.

An external SPI RAM acting as a frame buffer is attached to the SPI.

Here is the interesting part about the SPI RAM. There is an internal address generator, a shifter and a state machine to shift out the memory. That's pretty much most of the blocks in a video frame buffer nicely contained in a simple 8-pin package.

SPI SRAM timing

Once you have issue the "Read" command, the chip would sequentially read off the contents as long as the /CS line is assert and the clock is applied. So that's all the ARM chip need to do during the active part of the display. The MOSI line is ignored by the SPI RAM until the /CS is toggled for a new command.

The ARM has full access to the RAM when the display is inactive. The quad AND gates are used to buffer the signals as well as hide the activities from the monitor as some of them expect the signals to be at 0V. The "Enable" signal is what I used to control the "AND" gates.

Horizontal scanline timing

There is also something neat about the newer SPI RAM parts. They support a Quad Serial mode where it can access the memory 4-bit at a time. This allows a 4-bit video output with 16 colours (RGB and Intensity) graphic display. The part can be re-program with a "RSTIO" command and access in SPI.

SPI SRAM Quad Serial mode timing

Draw backs

Unfortunately, most of the SPI RAM are only rated for 20MHz. There are also some fancy non-volatile SPI memory (FRAM/NVSRAM) that are rated for much higher clock speeds, but they are more expensive and might have limited write cycles.

Dangerous Prototype uses the 23LC1024 in their Logic Pirate and managed to overclock the heck out of it. Coincidentally, they use the quad mode for "sniffing" the logic signals and SPI mode for reading it out.
The 23LC1024 being a higher density is probably built with a smaller geometry. There is also a 23A1024 for 1.7-2.2V (1.8V technology?). The 20MHz timing for the 3.3V version is likely to be more conservative.

The ARM have limited access to the SPI RAM and only when RAM is not driving the video. This happens in (525-480) = 45 lines 60 times a second. Furthermore, the SPI RAM is serial in nature with an overhead of 8-bit command + 24-bit address. i.e. 32 SPI clocks * 2 = 64 CPU clock cycles just to start a command and only 1 bit wide bus. I'll let you do the math.

Even the on the fly rendering that uses up 51% of the CPU cycles, but have full 32-bit 0 waits access sounds attractive. This was one of the reason why I tried out that rendering idea.