ChibiTerm - Discrete Video buffer

Projects / ChibiTerm  Original post date: 03/04/2016

Discrete driver

STM32F030 I/O doesn't have enough drive current for video signal, so I came up with the following design.
LTSpice file: here

Note: This design is only for logic level i.e. 0/1 signals. For an analog signal, the input needs to be AC coupled and R5 be replaced with a voltage divider to compensate for the VBE drop. Alternatively, a PNP voltage follower can be added to compensate for the drop.

The input signal is 3.3V CMOS buffered by an emitter follower with some additional parts to compensate for the transistor's parasitic capacitance. The input trace (in red) is scaled to 0.7V.

A separate 2.5V supply is used to power the video output. I plan to use using a TL431 shunt regulator commonly used on old VGA cards (as a precision reference voltage for video DAC).

This is what happens without R4/C1. The falling edge shows that there is excessive capacitive load and that drags down the input signal V2. Once the input goes to ground, the capacitance at Base/Emitter discharges and caused an undershoot.

Video waveform without R4/C1

This is what happens without R5. (R5 helps by providing extra current for the rising edge.)

Video waveform without R5

This is with all the parts in the design.

Video waveform with all parts

The 2N3904 can actually be quite fast once you have compensated for its huge parasitic capacitances and drive it with a low impedance source.

The buffer is designed for driving RGB signals simultaneously using separate series resistors (i.e. 3 sets of R2) for each of the channels. The output voltage level can be tweaked by playing with R2. Other termination schemes can be also be explored.

Driving transistors - The ugly truth about parasitic capacitances

Notice the amount of current going into the base of the transistor (to charge/discharge parasitic capitance) during the transition most of it flowing through the tiny 22pF capacitor!

Lesson to be learnt here: At fast edge rate, parasitics can't be overlooked.

Refining the design

I played around with the values in the circuit to change the 2.5V to a 3.3V supply as I have changed my mind on what to do about the voltage regulator.

New 3.3V only design

This is the waveform measured at the output on a breadboard. So the noise floor isn't ideal.

Video waveform on breadboard

I prototyped the buffer on a protoboard as the parasitic on the breadboard would be significant relative to C1. The waveform looks reasonable. The monitor for some reasons uses 68R for termination. Not the first monitor that I have seen not using 75R. So that kind of affects the amplitude a bit for the cheapskate driver. Realistically it doesn't matter too much as we are exactly trying to be colour accurate here. :P

VGA terminal prototype on breadboard and switchmode supply

This is the video output at the pin header on the new module on a PCB with the monitor plugged in. This is the blinking underscore cursor. There is a tiny bit of overshoot, but other than that this is a very clean signal. The signal level as before is a bit lower than the 700mV.

Video waveform on final PCB module - blinky cursor